1. Field of the Invention
This invention relates to a delta sigma modulator and an oversampling delta sigma type analog-digital converter, and more particularly to a delta sigma modulator using switched capacitors.
2. Description of the Related Art
There is a known oversampling type analog-digital converter circuit which uses a delta sigma modulator that makes a sampling frequency high to shift a quantize noise and a folding noise outside a signal band.
A conventional delta sigma modulator using switched capacitors, as shown in FIG. 6, comprises a capacitor 5 that is charged with an input signal voltage, switches 1 and 2 that are switched on with a clock phi1 going high during a charging period shown in FIG. 7 for charging the capacitor 5 with the input signal voltage, switches 3 and 4 that are switched on with a clock phi2 going high during an operation period shown in FIG. 7 for outputting the electric charge held in the capacitor 5, and a circuit consisting of a capacitor 6 and an operational amplifier 7 for integrating the input signal voltage. The delta sigma modulator further comprises a 1-bit analog-digital converter 8 for comparing the output voltage of the integrating circuit and a ground electric potential and outputting a 1-bit digital value according to the comparison, a flip-flop 9 that operates as a delay circuit for delaying the output of the analog-digital converter 8 by a period of one clock cycle, switches 10 and 11 for switching and outputting reference voltages +Vref and -Vref according to the delayed digital value, a capacitor 16 that is charged with one of the positive and negative reference voltages, switches 12 and 13 that are switched on with the clock phi1 and charge the capacitor 16 with one of the reference voltages switched by the switches 10 and 11, and switches 14 and 15 that are switched on with the clock phi2 and output the electric charge held in the capacitor 16 to the integrating circuit. The switches 10 and 11, the capacitor 16, the switches 12 and 13, and the switches 14 and 15 as a whole constitute a 1-bit digital-analog conversion circuit.
Next, the operation of the conventional delta sigma modulator will be described.
If the clock phi1 goes to a logic high level the charging period, as shown in FIG. 7, the switches 1 and 2 will be on and the capacitor 5 will be charged with the voltage Vin of the input signal. Either of switches 10 and 11 is on, depending on that the digital value delayed by the output of the 1-bit digital-analog conversion circuit is either 0 or 1. At this time, the switches 12 and 13 have been on by the clock phil. For this reason, the capacitor is charged with either of the voltage +Vref and -Vref of the reference, depending on that the digital data is either 0 or 1.
If the clock phi2 goes to a logic high level at the operation period, the switches 3, 4 and the switches 14, 15 will be on. Therefore, the capacitors 5 and 16 are connected in parallel, and the electric charges charged in the capacitors 5 and 16 are added to the electric charge held in the capacitor 6 by the operational amplifier 7. From this, a voltage of the sum of the input voltage Vin and either of the positive and negative reference voltage Vref is integrated. The integration result is compared with the ground electric potential by the 1-bit analog-digital converter 8, a 1-bit digital data of modulation output is outputted in accordance with the sign of the signal.
The above-described conventional delta sigma modulation circuit requires 4 kinds of power supplies, the positive and negative operation power supplies for operating the operational amplifier 7 and the comparator constituting the 1-bit analog-digital converter 8, and the positive and negative reference power supplies for the 1-bit digital-analog conversion circuit. Also, if there is a difference between the absolute values of the voltages of the positive and negative reference power supplies of the digital-analog conversion circuit, the feedback or the positive and negative step electric charge will be different and the spectrum of the output signal will be greatly influenced. FIG. 4 shows the spectrum of the output signal of a simulated result under an ideal condition with no difference between the absolute values of positive and negative step voltages, while FIG. 5 shows the spectrum of the output signal of a simulated result as under the condition as FIG. 4 with a difference of 10% between the absolute values of positive and negative step voltages. From this figure, it is found that the rate of the suppression of noise near the signal band, which is the characteristic of the delta sigma modulator, is reduced. For this reason, these positive and negative reference power supplies are required to be accurate power supplies in which the absolute values of the positive and negative reference voltages are equal. Therefore, the power supply circuit becomes complex and large in scale.
As means for overcoming this disadvantage, there is a delta sigma type A/D conversion circuit disclosed in Japanese Patent Application Laying Open No. 5-37383.
As shown in FIGS. 8A and 8B, this delta sigma type A/D conversion circuit tries to obtain the positive and negative reference levels whose absolute values are equal, by making use of the thrust-up or thrust-down to a GND level caused by a feedback capacitor 16, on the basis of the voltage -VR of a kind of reference power supply. However, the delta sigma type A/D conversion shown in FIG. 8A also requires three kinds of power supplies, power supplies for operation and the reference power supply, and this reference power supply is required to be a highly accurate power supply whose impedance is low enough to keep a constant voltage irrespective of noise caused by the charging and discharging of capacity load, so there is the disadvantage that the power supply circuit becomes complex and large in scale and the current consumption in this portion causes an increase in current consumption of the entire device. Also, in FIG. 8A there is required a logic circuit such as 80 for generating timing signals (.phi.1A to .phi.2B) controlling the feedback capacitor 16, so this will further increase the circuit scale and the current consumption.
Also, various efforts for improving the accuracy of modulation have been made, and for example, there has been investigated a delta sigma modulator such as disclosed in Japanese Patent Application Laying Open No. 6-120837 in which the order of modulation is increased and feedback is performed on the way.
However, in using the delta sigma modulator, miniaturization and low cost are most required in accordance with its field of application, and there are some cases where a delta sigma modulator of high order such as that disclosed in the above-described Japanese Patent Application Laying Open No. 6-120837 is not needed. When the delta sigma modulator is used in the modem of a facsimile, for example, size and cost have priority over accuracy.